1. Technical Field
The present invention relates to an array of vertical bipolar junction transistors. In particular, the invention may be advantageously used to form an array of selectors in a phase change memory device, without however being limited thereto.
2. Description of the Related Art
As is known, phase change memories are formed by memory cells connected at the intersections of bitlines and wordlines and comprising each a memory element and a selection element. A memory element comprises a phase change region made of a phase change material, i.e., a material that may be electrically switched between a generally amorphous and a generally crystalline state across the entire spectrum between completely amorphous and completely crystalline states.
Typical materials suitable for the phase change region of the memory elements include various chalcogenide elements. The state of the phase change materials is non-volatile, absent application of excess temperatures, such as those in excess of 150° C., for extended times. When the memory is set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until reprogrammed, even if power is removed.
Selection elements may be formed according to different technologies, for example they can be implemented by diodes, by MOS transistors or bipolar transistors.
U.S. Pat. No. 7,227,171 discloses a method for manufacturing bipolar type selection transistors in a phase change memory device. Although the process described therein is satisfactory, it is susceptible of improvement, in particular as regards the emitter formation. Furthermore, this known process does not provide for salicided junctions of the selection transistors, but only of the circuitry transistors.
To improve the above process, the inventors have devised a process including defining, in a semiconductor body, a plurality of active areas delimited by field insulation regions; forming a plurality of base regions in the active areas; forming a plurality of silicide protection strips extending transversely to the field insulation regions above the semiconductor body; forming a plurality of emitter regions in each active area on a first side of the silicide protection strips; forming base contact regions in each active areas on a second side of the silicide protection strips; and forming silicide regions on the emitter and base contact regions. Thus, in each active area, the silicide protection strips separate the emitter regions from the base contact regions.
However, with the continuous miniaturization of the circuits, there is the risk the lateral diffusion of the implants during the activation causes the emitter regions and the base contact regions to be very close or even short-circuited, thus causing unwanted leakages in the selection transistors.
This problem is clarified with reference to FIGS. 1-3, showing a portion of a memory device accommodating selection transistors. In these figures, a substrate 1 comprises a subcollector region 2 a first conductivity type (e.g., P+), a collector region 3 of the first conductivity type (here, P type) and a base region 4, overlying the collector region 3 and of a second conductivity type (here, N type). The subcollector region 2 and the collector region 3 extend at least in part below the field oxide regions 6 and are common to and shared by the entire memory device. The base regions 4 have a strip-like form and extend each in an own active area 5 of the matrix. The active areas 5, as visible from the top view of FIG. 1, have also a strip-like shape and are insulated from each other by field oxide regions 6 obtained by STI (Shallow Trench Insulation).
Above the surface of the substrate 1, silicide protection regions 10, e.g., of silicon nitride, extend perpendicularly to the field oxide regions 6; in each active area 5, base contact regions 11, of N+ type, extend within the base region 4 on one side of each silicide protection region 10 and emitter regions 12, of P type, extend within the base region 4 on the other side of each silicide protection region 10, so that each base contact region 11 is separated by the neighboring emitter regions 12 by a silicide protection region 10.
The base contact regions 11 and the emitter regions 12 are covered by silicide regions 15 and the surface of the substrate 1 is covered by a dielectric layer 16. Base plugs 17 and emitter plugs 18 extend through the dielectric layer 16 for electrically connecting the base contact regions 11 and the emitter regions 12, respectively.
In the described structure, the silicide protection regions 10 may have a width of 100 nm; the plugs 17 and 18 may have a width of 80 nm, the distance between adjacent silicide protection regions 10 may be 120 nm. With the indicated dimensions, considering the lateral diffusion of the doping agents and possible mask misalignments (FIG. 1 also shows the emitter implant mask 19), there is the risk that the base contact regions 11 and the emitter regions 12 come into contact and behave like Zener diodes, giving rise to current leakages, which is undesired.
US 2002/0081807 discloses a phase-change memory device having a dual trench isolation, wherein each selection element (a diode) is isolated from the adjacent ones in both directions by shallow trench regions. The upper region of the selection element is silicided. US 2002/0079483 and US 2002/0079524 disclose other phase-change memory devices having a dual trench isolation. These processes are particularly burdensome and cannot be used to manufacture transistors having at least two terminals connected to upper metal layers.